View source

Alpha Micro made a version of [[S-100 bus]] for 16-bit processor.

== Pinout ==
 1     (Component side)      50
 ==============================
 100     (Solder side)       51

{| {{border}}
! Pin !! Name          !! Type     !! Dir         !! Description
|-
| 1   || +8 V          || Power    || {{arrowr}}  || +8 Volts
|-
| 2   || +18 V         || Power    || {{arrowr}}  || +18 Volts
|-
| 3   || ----          || Fr panel || {{arrowr}}  || External Ready To Processor
|-
| 4   || /VI0          || Control  || {{arrowl}}  || Vector Interrupt Line 0
|-
| 5   || /VI1          || Control  || {{arrowl}}  || Vector Interrupt Line 1
|-
| 6   || /VI2          || Control  || {{arrowl}}  || Vector Interrupt Line 2
|-
| 7   || /VI3          || Control  || {{arrowl}}  || Vector Interrupt Line 3
|-
| 8   || /VI4          || Control  || {{arrowl}}  || Vector Interrupt Line 4
|-
| 9   || /VI5          || Control  || {{arrowl}}  || Vector Interrupt Line 5
|-
| 10  || /VI6          || Control  || {{arrowl}}  || Vector Interrupt Line 6
|-
| 11  || /VI7          || Control  || {{arrowl}}  || Vector Interrupt Line 7
|-
| 12  ||               ||          ||             ||
|-
| 13  ||               ||          ||             ||
|-
| 14  ||               ||          ||             ||
|-
| 15  ||               ||          ||             ||
|-
| 16  ||               ||          ||             ||
|-
| 17  ||               ||          ||             ||
|-
| 18  || ----          ||          ||             ||
|-
| 19  || ----          ||          ||             ||
|-
| 20  || ???           ||          ||             ||
|-
| 21  || ---           ||          ||             ||
|-
| 22  || ---           ||          ||             ||
|-
| 23  || ---           ||          ||             ||
|-
| 24  || phi2          || Clock    || {{arrowr}}  || Primary Processor Clock Line
|-
| 25  || /PSTVAL       ||          || ?           || ?
|-
| 26  || PHLDA         || Control  || {{arrowr}}  || Processor In Hold Condition
|-
| 27  || PWAIT         || Control  || {{arrowr}}  || Processor In Wait Condition
|-
| 28  || PINTE         || Control  || {{arrowr}}  || Processor Permits Interrupts When Active
|-
| 29  || A5            || Address  || {{arrowr}}  || Address Line 5
|-
| 30  || A4            || Address  || {{arrowr}}  || Address Line 4
|-
| 31  || A3            || Address  || {{arrowr}}  || Address Line 3
|-
| 32  || A15           || Address  || {{arrowr}}  || Address Line 15
|-
| 33  || A12           || Address  || {{arrowr}}  || Address Line 12
|-
| 34  || A9            || Address  || {{arrowr}}  || Address Line 9
|-
| 35  || DO1           || Data     || {{arrowr}}  || Data Output Line 1
|-
| 36  || DO0           || Data     || {{arrowr}}  || Data Output Line 0
|-
| 37  || A10           || Address  || {{arrowr}}  || Address Line 10
|-
| 38  || DO4           || Data     || {{arrowr}}  || Data Output Line 4
|-
| 39  || DO5           || Data     || {{arrowr}}  || Data Output Line 5
|-
| 40  || DO6           || Data     || {{arrowr}}  || Data Output Line 6
|-
| 41  || DI2           || Data     || {{arrowl}}  || Data Input Line 2
|-
| 42  || DI3           || Data     || {{arrowl}}  || Data Input Line 3
|-
| 43  || DI7           || Data     || {{arrowl}}  || Data Input Line 7
|-
| 44  || SM1           || State    || {{arrowr}}  || Processor Instruction Fetch Signal
|-
| 45  || SOUT          || State    || {{arrowr}}  || Processor I/O Write Signal
|-
| 46  || SINP          || State    || {{arrowr}}  || Processor I/O Read Signal
|-
| 47  || SMEMR         || State    || {{arrowr}}  || Processor Memory Read Signal
|-
| 48  ||               ||          ||             ||
|-
| 49  || CLOC          || Clock    || {{arrowr}}  || 2Mhz Clock Signal
|-
| 50  || GND           || Power    || {{arrow}}   || Logical And Power Ground
|-
| 51  || +8V           || Power    || {{arrowr}}  || +8 Volts
|-
| 52  || -16V          || Power    || {{arrowr}}  || -18 Volts
|-
| 53  || ???           ||          ||             ||
|-
| 54  || ???           ||          ||             ||
|-
| 55  || ???           ||          ||             ||
|-
| 56  || /DMAGR7       ||          ||             ||
|-
| 57  || /DMAGR6       ||          ||             ||
|-
| 58  || /DMAGR5       ||          ||             ||
|-
| 59  || /DMAGR4       ||          ||             ||
|-
| 60  || /DMAGR3       ||          ||             ||
|-
| 61  || /DMAGR2       ||          ||             ||
|-
| 62  || /DMAGR1       ||          ||             ||
|-
| 63  || /DMAGR0       ||          ||             ||
|-
| 64  || /DMARCVD      ||          ||             ||
|-
| 65  || ---           ||          ||             ||
|-
| 66  || ---           ||          ||             ||
|-
| 67  || ???           ||          ||             ||
|-
| 68  || MWRT          || Ctrl/frp || {{arrowr}}  || Memory Write From Processor Or Front Panel
|-
| 69  || ???           ||          ||             ||
|-
| 70  || ???           ||          ||             ||
|-
| 71  || ???           ||          ||             ||
|-
| 72  || ???           ||          ||             ||
|-
| 73  || ???           ||          ||             ||
|-
| 74  || /DMAREQ       ||          || ?           || DMA Request
|-
| 75  || /PRESET       || Control  || {{arrowl}}  || Forces Processor To Reset State
|-
| 76  || ???           ||          ||             ||
|-
| 77  || /PWR          || Control  || {{arrowr}}  || Active When Processor Writes (I/O Or Memory)
|-
| 78  || PDBIN         || Control  || {{arrowr}}  || Active When Processor Reads (I/O Or Memory)
|-
| 79  || A0            || Address  || {{arrowr}}  || Address Line 0
|-
| 80  || A1            || Address  || {{arrowr}}  || Address Line 1
|-
| 81  || A2            || Address  || {{arrowr}}  || Address Line 2
|-
| 82  || A6            || Address  || {{arrowr}}  || Address Line 6
|-
| 83  || A7            || Address  || {{arrowr}}  || Address Line 7
|-
| 84  || A8            || Address  || {{arrowr}}  || Address Line 8
|-
| 85  || A13           || Address  || {{arrowr}}  || Address Line 13
|-
| 86  || A14           || Address  || {{arrowr}}  || Address Line 14
|-
| 87  || A11           || Address  || {{arrowr}}  || Address Line 11
|-
| 88  || DO2           || Data     || {{arrowr}}  || Data Output Line 2
|-
| 89  || DO3           || Data     || {{arrowr}}  || Data Output Line 3
|-
| 90  || DO7           || Data     || {{arrowr}}  || Data Output Line 7
|-
| 91  || DI4           || Data     || {{arrowl}}  || Data Input Line 4
|-
| 92  || DI5           || Data     || {{arrowl}}  || Data Input Line 5
|-
| 93  || DI6           || Data     || {{arrowl}}  || Data Input Line 6
|-
| 94  || DI1           || Data     || {{arrowl}}  || Data Input Line 1
|-
| 95  || DI0           || Data     || {{arrowl}}  || Data Input Line 0
|-
| 96  || SINTA         || Control  || {{arrowr}}  || Acknowledge Signal For Pint Request
|-
| 97  || /SWO          || Control  || {{arrowr}}  || Processor In Write Status
|-
| 98  || ???           ||          ||             ||
|-
| 99  || /POC          || Ft panel || {{arrowr}}  || Power-On Clear Signal
|-
| 100 || GND           ||          || {{arrow}}   || Power And Signal Ground
|}

''Note: Direction is CPU/Frontpanel relative cards.''

== See also ==
* [[IEEE-696]]
* [[S-100 bus]]

== Contributors ==
* [[User:Joakim:Joakim Ögren]]

== Sources ==
* [http://retrotechnology.com/herbs_stuff/busalt.txt List of Altair/IMSAI S100 signals] by Herb Johnson
* [http://retrotechnology.com/herbs_stuff/s100bus.html S-100 and IEEE-696 Bus List] by Herbert R. Johnson

[[Category:Connector]]
[[Category:Bus]]
[[Category:Obsolete]]