Atari Parallel Bus Interface

From HwB

(Difference between revisions)

Latest revision as of 19:37, 25 March 2007

PBI = Parallel Bus Interface

Available on Atari 600XL & 800XL.

Pinout

1                                                                       49
o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o
o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o
2                                                                       50

Pin	Name	Description
1	GND	Ground
2	~EXTSEL	External Select
3	A0	CPU Address bus line 0
4	A1	CPU Address bus line 1
5	A2	CPU Address bus line 2
6	A3	CPU Address bus line 3
7	A4	CPU Address bus line 4
8	A5	CPU Address bus line 5
9	A6	CPU Address bus line 6
10	GND	Ground
11	A7	CPU Address bus line 7
12	A8	CPU Address bus line 8
13	A9	CPU Address bus line 9
14	A10	CPU Address bus line 10
15	A11	CPU Address bus line 11
16	A12	CPU Address bus line 12
17	A13	CPU Address bus line 13
18	A14	CPU Address bus line 14
19	GND	Ground
20	A15	CPU Address bus line
21	D0	CPU Data bus line 0
22	D1	CPU Data bus line 1
23	D2	CPU Data bus line 2
24	D3	CPU Data bus line 3
25	D4	CPU Data bus line 4
26	D5	CPU Data bus line 5
27	D6	CPU Data bus line 6
28	D7	CPU Data bus line 7
29	GND	Ground
30	GND	Ground
31	B02,Phi2	CPU Phase 2 clock
32	GND	Ground
33	NC	Reserved
34	~RST	Reset output
35	~IRQ	Interrupt request
36	~RDY	Ready input
37	NC	Reserved
38	~EXTENB	CPU External Enable
39	NC	Reserved
40	~REF	Refresh cycle
41	~CAS	Column Address Strobe
42	GND	Ground
43	~MPD	Math Pack (FP) Disable
44	~RAS	Row Address Strobe
45	GND	Ground
46	LR/~W	Latched read/write
47	+5V	+5 VDC (only 600XL. Not connected on 800XL)
48	+5V	+5 VDC (only 600XL. Not connected on 800XL)
49	AUDIO	Audio input
50	GND	Ground

Note: ~ = Active low.

Contributions

Joakim Ögren

Sources

Atari 8-Bit Computers: Frequently Asked Questions by Michael D. Current

@@ Line 10: / Line 10: @@
 {| {{border}}
-!Pin !! Name
+!Pin !! Name     !! Description
 |-
-|  1 || GND Ground
+|  1 || GND      || Ground
 |-
-|  2 || ~EXTSEL External Select
+|  2 || ~EXTSEL  || External Select
 |-
-|  3 || A0 CPU Address bus line
+|  3 || A0       || CPU Address bus line 0
 |-
-|  4 || A1 CPU Address bus line
+|  4 || A1       || CPU Address bus line 1
 |-
-|  5 || A2 CPU Address bus line
+|  5 || A2       || CPU Address bus line 2
 |-
-|  6 || A3 CPU Address bus line
+|  6 || A3       || CPU Address bus line 3
 |-
-|  7 || A4 CPU Address bus line
+|  7 || A4       || CPU Address bus line 4
 |-
-|  8 || A5 CPU Address bus line
+|  8 || A5       || CPU Address bus line 5
 |-
-|  9 || A6 CPU Address bus line
+|  9 || A6       || CPU Address bus line 6
 |-
-| 10 || GND Ground
+| 10 || GND      || Ground
 |-
-| 11 || A7 CPU Address bus line
+| 11 || A7       || CPU Address bus line 7
 |-
-| 12 || A8 CPU Address bus line
+| 12 || A8       || CPU Address bus line 8
 |-
-| 13 || A9 CPU Address bus line
+| 13 || A9       || CPU Address bus line 9
 |-
-| 14 || A10 CPU Address bus line
+| 14 || A10      || CPU Address bus line 10
 |-
-| 15 || A11 CPU Address bus line
+| 15 || A11      || CPU Address bus line 11
 |-
-| 16 || A12 CPU Address bus line
+| 16 || A12      || CPU Address bus line 12
 |-
-| 17 || A13 CPU Address bus line
+| 17 || A13      || CPU Address bus line 13
 |-
-| 18 || A14 CPU Address bus line
+| 18 || A14      || CPU Address bus line 14
 |-
-| 19 || GND Ground
+| 19 || GND      || Ground
 |-
-| 20 || A15 CPU Address bus line
+| 20 || A15      || CPU Address bus line
 |-
-| 21 || D0 CPU Data bus line
+| 21 || D0       || CPU Data bus line 0
 |-
-| 22 || D1 CPU Data bus line
+| 22 || D1       || CPU Data bus line 1
 |-
-| 23 || D2 CPU Data bus line
+| 23 || D2       || CPU Data bus line 2
 |-
-| 24 || D3 CPU Data bus line
+| 24 || D3       || CPU Data bus line 3
 |-
-| 25 || D4 CPU Data bus line
+| 25 || D4       || CPU Data bus line 4
 |-
-| 26 || D5 CPU Data bus line
+| 26 || D5       || CPU Data bus line 5
 |-
-| 27 || D6 CPU Data bus line
+| 27 || D6       || CPU Data bus line 6
 |-
-| 28 || D7 CPU Data bus line
+| 28 || D7       || CPU Data bus line 7
 |-
-| 29 || GND Ground
+| 29 || GND      || Ground
 |-
-| 30 || GND Ground
+| 30 || GND      || Ground
 |-
-| 31 || B02,Phi2 CPU Phase 2 clock
+| 31 || B02,Phi2 || CPU Phase 2 clock
 |-
-| 32 || GND Ground
+| 32 || GND      || Ground
 |-
-| 33 || NC Reserved
+| 33 || NC       || Reserved
 |-
-| 34 || ~RST Reset output
+| 34 || ~RST     || Reset output
 |-
-| 35 || ~IRQ Interrupt request
+| 35 || ~IRQ     || Interrupt request
 |-
-| 36 || ~RDY Ready input
+| 36 || ~RDY     || Ready input
 |-
-| 37 || NC Reserved
+| 37 || NC       || Reserved
 |-
-| 38 || ~EXTENB CPU External Enable
+| 38 || ~EXTENB  || CPU External Enable
 |-
-| 39 || NC Reserved
+| 39 || NC       || Reserved
 |-
-| 40 || ~REF Refresh cycle
+| 40 || ~REF     || Refresh cycle
 |-
-| 41 || ~CAS Column Address Strobe
+| 41 || ~CAS     || Column Address Strobe
 |-
-| 42 || GND Ground
+| 42 || GND      || Ground
 |-
-| 43 || ~MPD Math Pack (FP) Disable
+| 43 || ~MPD     || Math Pack (FP) Disable
 |-
-| 44 || ~RAS Row Address Strobe
+| 44 || ~RAS     || Row Address Strobe
 |-
-| 45 || GND Ground
+| 45 || GND      || Ground
 |-
-| 46 || LR/~W Latched read/write
+| 46 || LR/~W    || Latched read/write
 |-
-| 47 || 800XL: NC. 600XL: +5V
+| 47 || +5V      || +5 VDC (only [[600XL]]. Not connected on [[800XL]])
 |-
-| 48 || 800XL: NC. 600XL: +5V
+| 48 || +5V      || +5 VDC (only [[600XL]]. Not connected on [[800XL]])
 |-
-| 49 || Audio input
+| 49 || AUDIO    || Audio input
 |-
-| 50 || GND Ground
+| 50 || GND      || Ground
 |}
+''Note: ~ = Active low.''
 == Contributions ==