Atari 800 Right Cartridge

From HwB

(Difference between revisions)

Latest revision as of 10:29, 30 March 2007

Atari 800 cartridge slots

Available on Atari 800 (Right Cartrdige).

Pinout

A  B  C  D  E  F  H  J  K  L  M  N  P  R  S
o  o  o  o  o  o  o  o  o  o  o  o  o  o  o
o  o  o  o  o  o  o  o  o  o  o  o  o  o  o
1                                         15

1	R/~W	CPU read/write late
2	A3	CPU Address bus line
3	A2	CPU Address bus line
4	A1	CPU Address bus line
5	A0	CPU Address bus line
6	D4	CPU Data bus line
7	D5	CPU Data bus line
8	D2	CPU Data bus line
9	D1	CPU Data bus line
10	D0	CPU Data bus line
11	D6	CPU Data bus line
12	~S4	Chip Select--$8000 to $9FFF
13	+5V	+5 VDC
14	RD4	ROM present--$8000 to $9FFF
15	~CCTL	Cartridge control select
A	B02,Phi2	CPU Phase 2 clock
B	GND	Ground
C	A4	CPU Address bus line
D	A5	CPU Address bus line
E	A6	CPU Address bus line
F	A7	CPU Address bus line
H	A8	CPU Address bus line
J	A9	CPU Address bus line
K	A12	CPU Address bus line
L	D3	CPU Data bus line
M	D7	CPU Data bus line
N	A11	CPU Address bus line
P	A10	CPU Address bus line
R	R/~W	Read/write
S	B02,Phi2	CPU Phase 2 clock

Contributions

Joakim Ögren

Sources

Atari 8-Bit Computers: Frequently Asked Questions by Michael D. Current

@@ Line 1: / Line 1: @@
-{{todo}}
+[[Image:Atari_800_Cartridge_slots.jpg|thumb|Atari 800 cartridge slots]]
-[[Image:Atari_800_Cartridge.png|thumb|Atari 800 cartridge slots]]
 Available on Atari [[800]] (Right Cartrdige).
@@ Line 10: / Line 9: @@
 {| {{border}}
-|  1 || R/~W CPU read/write late
+|  1 || R/~W     || CPU read/write late
 |-
-|  2 || A3 CPU Address bus line
+|  2 || A3       || CPU Address bus line
 |-
-|  3 || A2 CPU Address bus line
+|  3 || A2       || CPU Address bus line
 |-
-|  4 || A1 CPU Address bus line
+|  4 || A1       || CPU Address bus line
 |-
-|  5 || A0 CPU Address bus line
+|  5 || A0       || CPU Address bus line
 |-
-|  6 || D4 CPU Data bus line
+|  6 || D4       || CPU Data bus line
 |-
-|  7 || D5 CPU Data bus line
+|  7 || D5       || CPU Data bus line
 |-
-|  8 || D2 CPU Data bus line
+|  8 || D2       || CPU Data bus line
 |-
-|  9 || D1 CPU Data bus line
+|  9 || D1       || CPU Data bus line
 |-
-| 10 || D0 CPU Data bus line
+| 10 || D0       || CPU Data bus line
 |-
-| 11 || D6 CPU Data bus line
+| 11 || D6       || CPU Data bus line
 |-
-| 12 || ~S4 Chip Select--$8000 to $9FFF
+| 12 || ~S4      || Chip Select--$8000 to $9FFF
 |-
-| 13 || +5V
+| 13 || +5V      || +5 VDC
 |-
-| 14 || RD4 ROM present--$8000 to $9FFF
+| 14 || RD4      || ROM present--$8000 to $9FFF
 |-
-| 15 || ~CCTL Cartridge control select
+| 15 || ~CCTL    || Cartridge control select
 |-
-|  A || B02,Phi2 CPU Phase 2 clock
+|  A || B02,Phi2 || CPU Phase 2 clock
 |-
-|  B || GND Ground
+|  B || GND      || Ground
 |-
-|  C || A4 CPU Address bus line
+|  C || A4       || CPU Address bus line
 |-
-|  D || A5 CPU Address bus line
+|  D || A5       || CPU Address bus line
 |-
-|  E || A6 CPU Address bus line
+|  E || A6       || CPU Address bus line
 |-
-|  F || A7 CPU Address bus line
+|  F || A7       || CPU Address bus line
 |-
-|  H || A8 CPU Address bus line
+|  H || A8       || CPU Address bus line
 |-
-|  J || A9 CPU Address bus line
+|  J || A9       || CPU Address bus line
 |-
-|  K || A12 CPU Address bus line
+|  K || A12      || CPU Address bus line
 |-
-|  L || D3 CPU Data bus line
+|  L || D3       || CPU Data bus line
 |-
-|  M || D7 CPU Data bus line
+|  M || D7       || CPU Data bus line
 |-
-|  N || A11 CPU Address bus line
+|  N || A11      || CPU Address bus line
 |-
-|  P || A10 CPU Address bus line
+|  P || A10      || CPU Address bus line
 |-
-|  R || R/~W Read/write
+|  R || R/~W     || Read/write
 |-
-|  S || B02,Phi2 CPU Phase 2 clock
+|  S || B02,Phi2 || CPU Phase 2 clock
 |}