JTAG

From HwB

(Difference between revisions)

Latest revision as of 18:20, 31 March 2007

Todo: This page needs some editing.

JTAG = Joint Test Action Group

1 JTAG Header for FPGA/CPLD Applications (Comcom Electronics Standard) pinout
2 Pinout (10 pin)
3 Pinout (12 pin)
4 Pinout (14 pin TX)
5 Pinout (14 pin ARM)
6 Pinout (20 pin ARM)
7 Technical description
- 7.1 TDI
- 7.2 TDO
- 7.3 TCK
- 7.4 TMS
- 7.5 TRST
8 Links
9 Standards
10 See also
11 Source
12 Contributions

JTAG Header for FPGA/CPLD Applications (Comcom Electronics Standard) pinout

Pin	Name	Description
1	TCK	Test Clock
2	GND	Ground
3	TDI	Test Data Input
4	GND	Ground
5	TDO	Test Data Output
6	VCC	Power Supply
7	TMS	Test Mode Select
8	TRS	Test Reset

[1]

Pinout (10 pin)

File:Idc10m.png

10 PIN IDC MALE at the CPU.

File:Idc10f.png

10 PIN IDC FEMALE at the cable/programmer.

Pin	Name	Description
1	TCK	Test Clock
2	GND	Ground
3	TDO	Test Data Output
4	VTref
5	TMS	Test Mode Select
6	nSRST	System Reset
7	Vsupply
8	NC	Not connected
9	TDI	Test Data Input
10	GND	Ground

Note: Direction is target (CPU) relative JTAG-bus (PC)

Pinout (12 pin)

12 PIN IDC 2x6 0.05" MALE at the CPU.

12 PIN IDC 2x6 0.05" FEMALE at the cable/programmer.

Pin	Name	Description
1	nTRST	JTAG Reset
2	GND	Ground
3	TDI	Test Data Input
4	GND	Ground
5	TDO	Test Data Output
6	GND	Ground
7	TMS	Test Mode Select
8	GND	Ground
9	TCK	Test Clock
10	GND	Ground
11	nSRST	System Reset
12	GND	Ground

MAJIC® Interface Specs for ARM Debug Interface and Intel XScale® Technology

Pinout (14 pin TX)

Used by Texas Instruments.

File:Idc14m.png

14 PIN IDC MALE at the CPU.

File:Idc14f.png

14 PIN IDC FEMALE at the cable/programmer.

Pin	Name	Description
1	TMS	Test Mode Select
2	nTRST	TAP reset
3	TDI	Test Data Input
4	GND	Ground
5	VCC	Power
6	n/c	Ground
7	TDO	Test Data Output
8	GND	Ground
9	RTCK	Test Clock?
10	GND	Ground
11	TCK	Test Clock
12	GND	Ground
13	nEMU0
14	nEMU1

Pinout (14 pin ARM)

File:Idc14m.png

14 PIN IDC MALE at the CPU.

File:Idc14f.png

14 PIN IDC FEMALE at the cable/programmer.

Pin	Name	Description
1	VCC
2	GND	Ground
3	nTRST
4	GND	Ground
5	TDI	Test Data Input
6	GND	Ground
7	TMS	Test Mode Select
8	GND	Ground
9	TCK	Test Clock
10	GND	Ground
11	TDO	Test Data Output
12	nSRST	Ground
13	VCC
14	GND	Ground

Pinout (20 pin ARM)

Used for ARM processors.

20 PIN IDC MALE at the CPU.

20 PIN IDC FEMALE at the cable/programmer.

Pin	Name	Description
1	VTref
2	GND or VSupply	Ground or VSupply
3	nTRST
4	GND	Ground
5	TDI	Test Data Input
6	GND	Ground
7	TMS	Test Mode Select
8	GND	Ground
9	TCK	Test Clock
10	GND	Ground
11	RTCK
12	GND	Ground
13	TDO	Test Data Output
14	GND	Ground
15	nSRST
16	GND	Ground
17	DBGRQ
18	GND	Ground
19	DBGACK
20	GND	Ground

Technical description

TDI

TDI = Test Data In

TDO

TDO = Test Data Out

TCK

TCK = Test Clock

TMS

TMS = Test Mode Select

TRST

TRST = Test ReSeT
Optional.

Links

Corelis: Boundary-Scan Tutorial

Standards

IEEE 1149.1-1990: Test Access Port and Boundary-Scan Architecture
IEEE 1149.1-1994b: Supplement to IEEE Std 1149.1-1990 (Boundary-Scan Description Language, BSDL)

Source

Contributions

Joakim Ögren

@@ Line 1: / Line 1: @@
 {{todo}}
 ''JTAG = Joint Test Action Group''
-== MIPS EJTAG 2.6 ==
-Found in Edimax routers
-{| {{border}}
-! Pin!! Name
-|-
-|  1 || nTRST
-|-
-|  2 || GND
-|-
-|  3 || TDI
-|-
-|  4 || GND
-|-
-|  5 || TDO
-|-
-|  6 || GND
-|-
-|  7 || TMS
-|-
-|  8 || GND
-|-
-|  9 || TCK
-|-
-| 10 || GND
-|-
-| 11 || nSRST
-|-
-| 12 || n/a
-|-
-| 13 || n/a
-|-
-| 14 || Vcc
-|}
-== MIPS Truncated EJTAG ==
-Seems, this header is a truncated version of the full EJTAG header.
-Found in Linksys routers such as the WRT54G and WRT54GS.
-{| {{border}}
-! Pin!! Name
-|-
-|  1 || nTRST
-|-
-|  2 || GND
-|-
-|  3 || TDI
-|-
-|  4 || GND
-|-
-|  5 || TDO
-|-
-|  6 || GND
-|-
-|  7 || TMS
-|-
-|  8 || GND
-|-
-|  9 || TCK
-|-
-| 10 || GND
-|-
-| 11 || nSRST
-|-
-| 12 || GND
-|}
-[http://www.mips.com/content/Documentation/MIPSDocumentation/EJTAG/doclibrary]
 == JTAG Header for FPGA/CPLD Applications (Comcom Electronics Standard) pinout ==
@@ Line 119: / Line 49: @@
 |  5 || TMS     || {{arrow}}  || Test Mode Select
 |-
-|  6 || nSRST   || {{arrow}}  ||
+|  6 || nSRST   || {{arrow}}  || System Reset
 |-
 |  7 || Vsupply || {{arrow}}  ||
@@ Line 189: / Line 119: @@
 |  1 || TMS     || {{arrow}}  || Test Mode Select
 |-
-|  2 || nTRST   || {{arrow}}  ||
+|  2 || nTRST   || {{arrow}}  || TAP reset
 |-
 |  3 || TDI     || {{arrow}}  || Test Data Input
@@ Line 195: / Line 125: @@
 |  4 || GND     || {{arrow}}  || Ground
 |-
-|  5 || VCC     || {{arrow}}  ||
+|  5 || VCC     || {{arrow}}  || Power
 |-
 |  6 || n/c     || {{arrow}}  || Ground
@@ Line 313: / Line 243: @@
 | 20 || GND            || {{arrow}}  || Ground
 |}
+== Technical description ==
+=== TDI ===
+''TDI = Test Data In''
+=== TDO ===
+''TDO = Test Data Out''
+=== TCK ===
+''TCK = Test Clock''
+=== TMS ===
+''TMS = Test Mode Select''
+=== TRST ===
+''TRST = Test ReSeT''<br/>
+Optional.
 == Links ==
@@ Line 320: / Line 263: @@
 * IEEE 1149.1-1990: Test Access Port and Boundary-Scan Architecture
 * IEEE 1149.1-1994b: Supplement to IEEE Std 1149.1-1990 (Boundary-Scan Description Language, BSDL)
+== See also ==
+* [[EJTAG]]
 == Source ==