Spectravideo SVI318/328 Expansion Bus

From HwB

(Difference between revisions)
 
 
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{| {{border}}
 
{| {{border}}
−
! Pin !! Name    !! Dir       !! Description
+
! Pin !! Name    !! Dir         !! Description
 
|-
 
|-
−
| 1  || +5v    || {{arrowr}} || Power, 300mA
+
| 1  || +5v    || {{arrowr}} || Power, 300mA
 
|-
 
|-
−
| 2  || /CNTRL2 || {{arrowl}} || Game adapter control signal
+
| 2  || /CNTRL2 || {{arrowl}} || Game adapter control signal
 
|-
 
|-
−
| 3  || +12v    || {{arrowr}} || Power, 100mA
+
| 3  || +12v    || {{arrowr}} || Power, 100mA
 
|-
 
|-
−
| 4  || -12v    || {{arrowr}} || Power, 50mA
+
| 4  || -12v    || {{arrowr}} || Power, 50mA
 
|-
 
|-
−
| 5  || /CNTRL1 || {{arrowl}} || Game adapter control signal
+
| 5  || /CNTRL1 || {{arrowl}} || Game adapter control signal
 
|-
 
|-
−
| 6  || /WAIT  || {{arrowl}} || Z80 WAIT
+
| 6  || /WAIT  || {{arrowl}} || Z80 WAIT
 
|-
 
|-
−
| 7  || /RST    || {{arrowl}} || Z80 RST
+
| 7  || /RST    || {{arrowl}} || Z80 RST
 
|-
 
|-
−
| 8  || CPU CLK || {{arrowr}} || Buffered 3.58MHz system clock
+
| 8  || CPU CLK || {{arrowr}} || Buffered 3.58MHz system clock
 
|-
 
|-
−
| 9  || A15    || {{arrowr}} || Buffered Address bus
+
| 9  || A15    || {{arrowr}} || Buffered Address bus
 
|-
 
|-
−
| 10  || A14    || {{arrowr}} || "
+
| 10  || A14    || {{arrowr}} || "
 
|-
 
|-
−
| 11  || A13    || {{arrowr}} || "
+
| 11  || A13    || {{arrowr}} || "
 
|-
 
|-
−
| 12  || A12    || {{arrowr}} || "
+
| 12  || A12    || {{arrowr}} || "
 
|-
 
|-
−
| 13  || A11    || {{arrowr}} || "
+
| 13  || A11    || {{arrowr}} || "
 
|-
 
|-
−
| 14  || A10    || {{arrowr}} || "
+
| 14  || A10    || {{arrowr}} || "
 
|-
 
|-
−
| 15  || A9      || {{arrowr}} || "
+
| 15  || A9      || {{arrowr}} || "
 
|-
 
|-
−
| 16  || A8      || {{arrowr}} || "
+
| 16  || A8      || {{arrowr}} || "
 
|-
 
|-
−
| 17  || A7      || {{arrowr}} || "
+
| 17  || A7      || {{arrowr}} || "
 
|-
 
|-
−
| 18  || A6      || {{arrowr}} || "
+
| 18  || A6      || {{arrowr}} || "
 
|-
 
|-
−
| 19  || A5      || {{arrowr}} || "
+
| 19  || A5      || {{arrowr}} || "
 
|-
 
|-
−
| 20  || A4      || {{arrowr}} || "
+
| 20  || A4      || {{arrowr}} || "
 
|-
 
|-
−
| 21  || A3      || {{arrowr}} || "
+
| 21  || A3      || {{arrowr}} || "
 
|-
 
|-
−
| 22  || A2      || {{arrowr}} || "
+
| 22  || A2      || {{arrowr}} || "
 
|-
 
|-
−
| 23  || A1      || {{arrowr}} || "
+
| 23  || A1      || {{arrowr}} || "
 
|-
 
|-
−
| 24  || A0      || {{arrowr}} || "
+
| 24  || A0      || {{arrowr}} || "
 
|-
 
|-
−
| 25  || /RFSH  || {{arrowr}} || RAM expansion refresh
+
| 25  || /RFSH  || {{arrowr}} || RAM expansion refresh
 
|-
 
|-
−
| 26  || /EXCSR  || {{arrowl}} || Video-CPU write select
+
| 26  || /EXCSR  || {{arrowl}} || Video-CPU write select
 
|-
 
|-
−
| 27  || /M1    || {{arrowr}} || Z80 M1
+
| 27  || /M1    || {{arrowr}} || Z80 M1
 
|-
 
|-
−
| 28  || /EXCSW  || {{arrowl}} || CPU-Video write select
+
| 28  || /EXCSW  || {{arrowl}} || CPU-Video write select
 
|-
 
|-
−
| 29  || /WR    || {{arrowr}} || Z80 WR
+
| 29  || /WR    || {{arrowr}} || Z80 WR
 
|-
 
|-
−
| 30  || /MREQ  || {{arrowr}} || Z80 MREQ
+
| 30  || /MREQ  || {{arrowr}} || Z80 MREQ
 
|-
 
|-
−
| 31  || /IORQ  || {{arrowr}} || Z80 IORQ
+
| 31  || /IORQ  || {{arrowr}} || Z80 IORQ
 
|-
 
|-
−
| 32  || /RD    || {{arrowr}} || Z80 RD
+
| 32  || /RD    || {{arrowr}} || Z80 RD
 
|-
 
|-
−
| 33  || D0      || I/O        || Buffered Data Bus
+
| 33  || D0      || {{arrowlr}} || Buffered Data Bus
 
|-
 
|-
−
| 34  || D1      || I/O        || "
+
| 34  || D1      || {{arrowlr}} || "
 
|-
 
|-
−
| 35  || D2      || I/O        || "
+
| 35  || D2      || {{arrowlr}} || "
 
|-
 
|-
−
| 36  || D3      || I/O        || "
+
| 36  || D3      || {{arrowlr}} || "
 
|-
 
|-
−
| 37  || D4      || I/O        || "
+
| 37  || D4      || {{arrowlr}} || "
 
|-
 
|-
−
| 38  || D5      || I/O        || "
+
| 38  || D5      || {{arrowlr}} || "
 
|-
 
|-
−
| 39  || D6      || I/O        || "
+
| 39  || D6      || {{arrowlr}} || "
 
|-
 
|-
−
| 40  || D7      || I/O        || "
+
| 40  || D7      || {{arrowlr}} || "
 
|-
 
|-
−
| 41  || CSOUND  || {{arrowl}} || Audio input signal
+
| 41  || CSOUND  || {{arrowl}} || Audio input signal
 
|-
 
|-
−
| 42  || /INT    || {{arrowl}} || Z80 INT
+
| 42  || /INT    || {{arrowl}} || Z80 INT
 
|-
 
|-
−
| 43  || /RAMDIS || {{arrowl}} || Disable user RAM
+
| 43  || /RAMDIS || {{arrowl}} || Disable user RAM
 
|-
 
|-
−
| 44  || /ROMDIS || {{arrowl}} || Disable basic ROM
+
| 44  || /ROMDIS || {{arrowl}} || Disable basic ROM
 
|-
 
|-
−
| 45  || /BK32  || {{arrowr}} || Enable bank 32 Memory (8000-ffff)
+
| 45  || /BK32  || {{arrowr}} || Enable bank 32 Memory (8000-ffff)
 
|-
 
|-
−
| 46  || /BK31  || {{arrowr}} || Enable bank 31 Memory (0000-7FFF)
+
| 46  || /BK31  || {{arrowr}} || Enable bank 31 Memory (0000-7FFF)
 
|-
 
|-
−
| 47  || /BK22  || {{arrowr}} || Enable bank 22 Memory (8000-FFFF)
+
| 47  || /BK22  || {{arrowr}} || Enable bank 22 Memory (8000-FFFF)
 
|-
 
|-
−
| 48  || /BK21  || {{arrowr}} || Enable bank 21 Memory (0000-7FFF)
+
| 48  || /BK21  || {{arrowr}} || Enable bank 21 Memory (0000-7FFF)
 
|-
 
|-
−
| 49  || GND    || -          || System Ground
+
| 49  || GND    || {{arrow}}  || System Ground
 
|-
 
|-
−
| 50  || GND    || -          || System Ground
+
| 50  || GND    || {{arrow}}  || System Ground
 
|}
 
|}
  
 
== Contributions ==
 
== Contributions ==
−
 
 
* [mailto:[email protected] Rob Gill]
 
* [mailto:[email protected] Rob Gill]
 
* [[User:Joakim|Joakim Ögren]]
 
* [[User:Joakim|Joakim Ögren]]
  
 
== Sources ==
 
== Sources ==
−
 
 
* SVI 328 Mk II User Manual
 
* SVI 328 Mk II User Manual
  
 
[[Category:Connector]]
 
[[Category:Connector]]
 +
[[Category:Bus]]

Latest revision as of 15:50, 29 March 2007

Spectravideo SVI-605 (Super Expander) can be connected to this bus.

Pinout

Unknown.png

50 PIN MALE EDGE the computer.

Pin Name Dir Description
1 +5v Arrowr.png Power, 300mA
2 /CNTRL2 Arrowl.png Game adapter control signal
3 +12v Arrowr.png Power, 100mA
4 -12v Arrowr.png Power, 50mA
5 /CNTRL1 Arrowl.png Game adapter control signal
6 /WAIT Arrowl.png Z80 WAIT
7 /RST Arrowl.png Z80 RST
8 CPU CLK Arrowr.png Buffered 3.58MHz system clock
9 A15 Arrowr.png Buffered Address bus
10 A14 Arrowr.png "
11 A13 Arrowr.png "
12 A12 Arrowr.png "
13 A11 Arrowr.png "
14 A10 Arrowr.png "
15 A9 Arrowr.png "
16 A8 Arrowr.png "
17 A7 Arrowr.png "
18 A6 Arrowr.png "
19 A5 Arrowr.png "
20 A4 Arrowr.png "
21 A3 Arrowr.png "
22 A2 Arrowr.png "
23 A1 Arrowr.png "
24 A0 Arrowr.png "
25 /RFSH Arrowr.png RAM expansion refresh
26 /EXCSR Arrowl.png Video-CPU write select
27 /M1 Arrowr.png Z80 M1
28 /EXCSW Arrowl.png CPU-Video write select
29 /WR Arrowr.png Z80 WR
30 /MREQ Arrowr.png Z80 MREQ
31 /IORQ Arrowr.png Z80 IORQ
32 /RD Arrowr.png Z80 RD
33 D0 Arrowlr.png Buffered Data Bus
34 D1 Arrowlr.png "
35 D2 Arrowlr.png "
36 D3 Arrowlr.png "
37 D4 Arrowlr.png "
38 D5 Arrowlr.png "
39 D6 Arrowlr.png "
40 D7 Arrowlr.png "
41 CSOUND Arrowl.png Audio input signal
42 /INT Arrowl.png Z80 INT
43 /RAMDIS Arrowl.png Disable user RAM
44 /ROMDIS Arrowl.png Disable basic ROM
45 /BK32 Arrowr.png Enable bank 32 Memory (8000-ffff)
46 /BK31 Arrowr.png Enable bank 31 Memory (0000-7FFF)
47 /BK22 Arrowr.png Enable bank 22 Memory (8000-FFFF)
48 /BK21 Arrowr.png Enable bank 21 Memory (0000-7FFF)
49 GND Arrow.png System Ground
50 GND Arrow.png System Ground

Contributions

Sources

  • SVI 328 Mk II User Manual
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