CTIA

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(Difference between revisions)
(New page: ''CTIA = Color Television Interface Adapter'' CTIA is a television interface chip. It's available on early NTSC Atari 400 & 800. Later models shipped with GTIA. [[Catego...)
 
 
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''CTIA = Color Television Interface Adapter''  
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''CGIA = Color Graphics Interface Adapter''  
  
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CTIA is a television interface chip. It's available on early NTSC [[Atari]] [[400]] & [[800]]. Later models shipped with [[GTIA]].
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CGIA is a television interface chip. It's available on early NTSC [[Atari]] [[400]] & [[800]]. Later models shipped with [[GTIA]].
 +
 
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== Pinout ==
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{| {{border}}
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! Pin !! Name        !! Direction  !! Description
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|-
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| 1  || OSC          || I          || Master clock input (typically 3.579 MHz)
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|-
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| 2  || S0          || I          || Switch I/O line 0
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|-
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| 3  || S1          || I          || Switch I/O line 1
 +
|-
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| 4  || COL          || O          || Color frequency ouput signal
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|-
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| 5  || S2          || I          || Switch I/O line 2
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|-
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| 6  || S3          || I          || Switch I/O line 3
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|-
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| 7  || n/c          || -          || not connected
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|-
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| 8  || VCC          || I          || Positive voltage power supply (+5.0 VDC)
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|-
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| 9  || CLUM        || O          || Analog video output signal
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|-
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| 10  || T0          || I          || Data input lines (from joystick controllers)
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|-
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| 11  || T1          || I          || Data input lines (from joystick controllers)
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|-
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| 12  || T2          || I          || Data input lines (from joystick controllers)
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|-
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| 13  || T3          || I          || Data input lines (from joystick controllers)
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|-
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| 14  || A0          || I/O        || Address bus line 0
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|-
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| 15  || A5          || O          || Address bus line 5
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|-
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| 16  || A6          || O          || Address bus line 6
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|-
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| 17  || A7          || O          || Address bus line 7
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|-
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| 18  || A8          || I/O        || Address bus line 8
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|-
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| 19  || A9          || I/O        || Address bus line 9
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|-
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| 20  || A10          || I/O        || Address bus line 10
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|-
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| 21  || A11          || I/O        || Address bus line 11
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|-
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| 22  || A12          || I/O        || Address bus line 12
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|-
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| 23  || A13          || I/O        || Address bus line 13
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|-
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| 24  || A14          || I/O        || Address bus line 14
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|-
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| 25  || A15          || I/O        || Address bus line 15
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|-
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| 26  || D0          || I/O        || Data I/O line 0
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|-
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| 27  || D1          || I/O        || Data I/O line 1
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|-
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| 28  || D2          || I/O        || Data I/O line 2
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|-
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| 29  || D3          || I/O        || Data I/O line 3
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|-
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| 30  || D4          || I/O        || Data I/O line 4
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|-
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| 31  || D5          || I/O        || Data I/O line 5
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|-
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| 32  || D6          || I/O        || Data I/O line 6
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|-
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| 33  || D7          || I/O        || Data I/O line 7
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|-
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| 34  || /NMI        || O          || Non-maskable interrupt
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|-
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| 35  || /LP          || I          || Signal from Lightpen
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|-
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| 36  || VSS          || I          || Power supply ground
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|-
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| 37  || /RNMI        || I          || Non-maskable interrupt
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|-
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| 38  || RDY          || O          || Ready
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|-
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| 39  || /REF        || O          || RAM refresh
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|-
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| 40  || /HALT        || O          || Halt
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|-
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| 41  || /RES        || I          || Reset
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|-
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| 42  || Φ0      || O          || Phase zero output for 6502 microprocessor
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|-
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| 43  || R/W          || I/O        || Controls direction of data transfers
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|-
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| 44  || A1          || I/O        || Address bus line 1
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|-
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| 45  || A2          || I/O        || Address bus line 2
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|-
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| 46  || A3          || I/O        || Address bus line 3
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|-
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| 47  || A4          || I/O        || Address bus line 4
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|-
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| 48  || Φ2      || I          || Phase two microprocessor clock from 6502 MPU
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|}
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== Source ==
 +
* [http://www.retromicro.com/files/atari/8bit/cgia.pdf CGIA datasheet]
  
 
[[Category:Chip]]
 
[[Category:Chip]]

Latest revision as of 21:56, 18 July 2008

CGIA = Color Graphics Interface Adapter

CGIA is a television interface chip. It's available on early NTSC Atari 400 & 800. Later models shipped with GTIA.

Pinout

Pin Name Direction Description
1 OSC I Master clock input (typically 3.579 MHz)
2 S0 I Switch I/O line 0
3 S1 I Switch I/O line 1
4 COL O Color frequency ouput signal
5 S2 I Switch I/O line 2
6 S3 I Switch I/O line 3
7 n/c - not connected
8 VCC I Positive voltage power supply (+5.0 VDC)
9 CLUM O Analog video output signal
10 T0 I Data input lines (from joystick controllers)
11 T1 I Data input lines (from joystick controllers)
12 T2 I Data input lines (from joystick controllers)
13 T3 I Data input lines (from joystick controllers)
14 A0 I/O Address bus line 0
15 A5 O Address bus line 5
16 A6 O Address bus line 6
17 A7 O Address bus line 7
18 A8 I/O Address bus line 8
19 A9 I/O Address bus line 9
20 A10 I/O Address bus line 10
21 A11 I/O Address bus line 11
22 A12 I/O Address bus line 12
23 A13 I/O Address bus line 13
24 A14 I/O Address bus line 14
25 A15 I/O Address bus line 15
26 D0 I/O Data I/O line 0
27 D1 I/O Data I/O line 1
28 D2 I/O Data I/O line 2
29 D3 I/O Data I/O line 3
30 D4 I/O Data I/O line 4
31 D5 I/O Data I/O line 5
32 D6 I/O Data I/O line 6
33 D7 I/O Data I/O line 7
34 /NMI O Non-maskable interrupt
35 /LP I Signal from Lightpen
36 VSS I Power supply ground
37 /RNMI I Non-maskable interrupt
38 RDY O Ready
39 /REF O RAM refresh
40 /HALT O Halt
41 /RES I Reset
42 Φ0 O Phase zero output for 6502 microprocessor
43 R/W I/O Controls direction of data transfers
44 A1 I/O Address bus line 1
45 A2 I/O Address bus line 2
46 A3 I/O Address bus line 3
47 A4 I/O Address bus line 4
48 Φ2 I Phase two microprocessor clock from 6502 MPU

Source

Retrieved from "http://www.hardwarebook.info/index.php?title=CTIA&oldid=9026"