Atari 8-bit Cartridge

From HwB

(Difference between revisions)

Revision as of 19:03, 25 March 2007

Available on Atari 400, 800 (Left Cartrdige), 1200XL, 600XL, 800XL, 65XE, 130XE, 800XE and the XE Game System.

Pinout

A  B  C  D  E  F  H  J  K  L  M  N  P  R  S
o  o  o  o  o  o  o  o  o  o  o  o  o  o  o
o  o  o  o  o  o  o  o  o  o  o  o  o  o  o
1                                         15

Pin	Name	Description
1	~S4	Chip Select ($8000 to $9FFF)
2	A3	CPU Address bus line 3
3	A2	CPU Address bus line 2
4	A1	CPU Address bus line 1
5	A0	CPU Address bus line 0
6	D4	CPU Data bus line 4
7	D5	CPU Data bus line 5
8	D2	CPU Data bus line 2
9	D1	CPU Data bus line 1
10	D0	CPU Data bus line 0
11	D6	CPU Data bus line 6
12	~S5	Chip Select ($A000 to $BFFF)
13	+5V	+5 VDC
14	RD5	ROM present ($A000 to $BFFF)
15	~CCTL	Cartridge control select
A	RD4	ROM present ($8000 to $9FFF)
B	GND	Ground
C	A4	CPU Address bus line 4
D	A5	CPU Address bus line 5
E	A6	CPU Address bus line 6
F	A7	CPU Address bus line 7
H	A8	CPU Address bus line 8
J	A9	CPU Address bus line 9
K	A12	CPU Address bus line 12
L	D3	CPU Data bus line 3
M	D7	CPU Data bus line 7
N	A11	CPU Address bus line 11
P	A10	CPU Address bus line 10
R	R/~W	CPU read/write
S	B02,Phi2	CPU Phase 2 clock

Note: ~ = Active low.

Contributions

Joakim Ögren

Sources

Atari 8-Bit Computers: Frequently Asked Questions by Michael D. Current

@@ Line 1: / Line 1: @@
-{{todo}}
 Available on Atari [[400]], [[800]] (Left Cartrdige), [[1200XL]], [[600XL]], [[800XL]], [[65XE]], [[130XE]], [[800XE]] and the [[XE Game System]].
@@ Line 9: / Line 8: @@
 {| {{border}}
-|  1 || ~S4 Chip Select--$8000 to $9FFF
+! Pin!! Name     !! Description
 |-
-|  2 || A3 CPU Address bus line
+|  1 || ~S4      || Chip Select ($8000 to $9FFF)
 |-
-|  3 || A2 CPU Address bus line
+|  2 || A3       || CPU Address bus line 3
 |-
-|  4 || A1 CPU Address bus line
+|  3 || A2       || CPU Address bus line 2
 |-
-|  5 || A0 CPU Address bus line
+|  4 || A1       || CPU Address bus line 1
 |-
-|  6 || D4 CPU Data bus line
+|  5 || A0       || CPU Address bus line 0
 |-
-|  7 || D5 CPU Data bus line
+|  6 || D4       || CPU Data bus line 4
 |-
-|  8 || D2 CPU Data bus line
+|  7 || D5       || CPU Data bus line 5
 |-
-|  9 || D1 CPU Data bus line
+|  8 || D2       || CPU Data bus line 2
 |-
-| 10 || D0 CPU Data bus line
+|  9 || D1       || CPU Data bus line 1
 |-
-| 11 || D6 CPU Data bus line
+| 10 || D0       || CPU Data bus line 0
 |-
-| 12 || ~S5 Chip Select--$A000 to $BFFF
+| 11 || D6       || CPU Data bus line 6
 |-
-| 13 || +5V
+| 12 || ~S5      || Chip Select ($A000 to $BFFF)
 |-
-| 14 || RD5 ROM present--$A000 to $BFFF
+| 13 || +5V      || +5 VDC
 |-
-| 15 || ~CCTL Cartridge control select
+| 14 || RD5      || ROM present ($A000 to $BFFF)
 |-
-|  A || RD4 ROM present--$8000 to $9FFF
+| 15 || ~CCTL    || Cartridge control select
 |-
-|  B || GND Ground
+|  A || RD4      || ROM present ($8000 to $9FFF)
 |-
-|  C || A4 CPU Address bus line
+|  B || GND      || Ground
 |-
-|  D || A5 CPU Address bus line
+|  C || A4       || CPU Address bus line 4
 |-
-|  E || A6 CPU Address bus line
+|  D || A5       || CPU Address bus line 5
 |-
-|  F || A7 CPU Address bus line
+|  E || A6       || CPU Address bus line 6
 |-
-|  H || A8 CPU Address bus line
+|  F || A7       || CPU Address bus line 7
 |-
-|  J || A9 CPU Address bus line
+|  H || A8       || CPU Address bus line 8
 |-
-|  K || A12 CPU Address bus line
+|  J || A9       || CPU Address bus line 9
 |-
-|  L || D3 CPU Data bus line
+|  K || A12      || CPU Address bus line 12
 |-
-|  M || D7 CPU Data bus line
+|  L || D3       || CPU Data bus line 3
 |-
-|  N || A11 CPU Address bus line
+|  M || D7       || CPU Data bus line 7
 |-
-|  P || A10 CPU Address bus line
+|  N || A11      || CPU Address bus line 11
 |-
-|  R || R/~W CPU read/write
+|  P || A10      || CPU Address bus line 10
 |-
-|  S || B02,Phi2 CPU Phase 2 clock
+|  R || R/~W     || CPU read/write
+|-
+|  S || B02,Phi2 || CPU Phase 2 clock
 |}
+''Note: ~ = Active low.''
 == Contributions ==