TI-99/4A Side Port

From HwB

(Difference between revisions)

Latest revision as of 15:47, 29 March 2007

Available on TI-99/4A computers. On the right side

Pinout

  2                             44
+----------------------------------+
| ================================ |
+----------------------------------+
  1                             43

Pin	Name	Description
1	VCC	+5 Volts power supply
2	SBE	Low if addr in >9000-94xx (sound port)
3	RESET*	System reset (active low)
4	EXTINT*	External interrupt (active low)
5	A5	Address bus, bit 5
6	A10	Address bus, bit 10
7	A4	Address bus, bit 4
8	A11	Address bus, bit 11
9	DBIN	Active high = read memory
10	A3	Address bus, bit 3
11	A12	Address bus, bit 12
12	READY	Active high = memory is ready
13	LOAD*	Unmaskable interrupt (=> BLWP @>FFFC)
14	A8	Address bus, bit 8
15	A13	Address bus, bit 13
16	A14	Address bus, bit 14
17	A7	Address bus, bit 7
18	A9	Address bus, bit 9
19	A15	Address bus, lsb. Also CRU output bit.
20	A2	Address bus, bit 2
21	GND	Ground
22	CRUCLK*	Inversion of TMS9900 CRUCLOCK pin
23	GND	Ground
24	PHI3*	Inversion of phase 3 clock
25	GND	Ground
26	WE*	Write Enable (derived from TMS9900 WE* pin)
27	GND	Ground
28	MBE*	Active low if addr in >4000-5FFF (card ROMs)
29	A6	Address bus, bit 6
30	A1	Address bus, bit 1
31	A0	Address bus, bit 0 (most significant)
32	MEMEN*	Memory access enable (active low)
33	CRUIN	CRU input bit to TMS9900
34	D7	Data bus, bit 7 (least significant)
35	D4	Data bus, bit 4
36	D6	Data bus, bit 6
37	D0	Data bus, bit 0 (most significant)
38	D5	Data bus, bit 5
39	D2	Data bus, bit 2
40	D1	Data bus, bit 1
41	IAQ	Interrupt acknowledged by TMS9900
42	D3	Data bus, bit 3
43	VDD	-5 Volts power supply
44	AUDIOIN	To sound generator AUDIO IN pin

Note: Direction is computer relative device.

Note: * = active low.

Caution: Bit 0 being MSB is strange.

Contributions

Joakim Ögren

@@ Line 22: / Line 22: @@
 | 5   || A5      || {{arrowr}}  || Address bus, bit 5
 |-
-| 6   || A10     || {{arrowr}}  || -
+| 6   || A10     || {{arrowr}}  || Address bus, bit 10
 |-
-| 7   || A4      || {{arrowr}}  || -
+| 7   || A4      || {{arrowr}}  || Address bus, bit 4
 |-
-| 8   || A11     || {{arrowr}}  || -
+| 8   || A11     || {{arrowr}}  || Address bus, bit 11
 |-
 | 9   || DBIN    || {{arrowr}}  || Active high = read memory
 |-
-| 10  || A3      || {{arrowr}}  || -
+| 10  || A3      || {{arrowr}}  || Address bus, bit 3
 |-
-| 11  || A12     || {{arrowr}}  || -
+| 11  || A12     || {{arrowr}}  || Address bus, bit 12
 |-
 | 12  || READY   || {{arrowl}}  || Active high = memory is ready
@@ Line 38: / Line 38: @@
 | 13  || LOAD*   || {{arrowl}}  || Unmaskable interrupt (=> BLWP @>FFFC)
 |-
-| 14  || A8      || {{arrowr}}  || -
+| 14  || A8      || {{arrowr}}  || Address bus, bit 8
 |-
-| 15  || A13     || {{arrowr}}  || -
+| 15  || A13     || {{arrowr}}  || Address bus, bit 13
 |-
-| 16  || A14     || {{arrowr}}  || -
+| 16  || A14     || {{arrowr}}  || Address bus, bit 14
 |-
-| 17  || A7      || {{arrowr}}  || -
+| 17  || A7      || {{arrowr}}  || Address bus, bit 7
 |-
-| 18  || A9      || {{arrowr}}  || -
+| 18  || A9      || {{arrowr}}  || Address bus, bit 9
 |-
 | 19  || A15     || {{arrowr}}  || Address bus, lsb. Also CRU output bit.
 |-
-| 20  || A2      || {{arrowr}}  || -
+| 20  || A2      || {{arrowr}}  || Address bus, bit 2
 |-
 | 21  || GND     || {{arrow}}   || Ground
@@ Line 68: / Line 68: @@
 | 28  || MBE*    || {{arrowr}}  || Active low if addr in >4000-5FFF (card ROMs)
 |-
-| 29  || A6      || {{arrowr}}  || -
+| 29  || A6      || {{arrowr}}  || Address bus, bit 6
 |-
-| 30  || A1      || {{arrowr}}  || -
+| 30  || A1      || {{arrowr}}  || Address bus, bit 1
 |-
 | 31  || A0      || {{arrowr}}  || Address bus, bit 0 (most significant)
@@ Line 80: / Line 80: @@
 | 34  || D7      || {{arrowlr}} || Data bus, bit 7 (least significant)
 |-
-| 35  || D4      || {{arrowlr}} || -
+| 35  || D4      || {{arrowlr}} || Data bus, bit 4
 |-
-| 36  || D6      || {{arrowlr}} || -
+| 36  || D6      || {{arrowlr}} || Data bus, bit 6
 |-
 | 37  || D0      || {{arrowlr}} || Data bus, bit 0 (most significant)
 |-
-| 38  || D5      || {{arrowlr}} || -
+| 38  || D5      || {{arrowlr}} || Data bus, bit 5
 |-
-| 39  || D2      || {{arrowlr}} || -
+| 39  || D2      || {{arrowlr}} || Data bus, bit 2
 |-
-| 40  || D1      || {{arrowlr}} || -
+| 40  || D1      || {{arrowlr}} || Data bus, bit 1
 |-
 | 41  || IAQ     || {{arrowl}}  || Interrupt acknowledged by TMS9900
 |-
-| 42  || D3      || {{arrowlr}} || -
+| 42  || D3      || {{arrowlr}} || Data bus, bit 3
 |-
 | 43  || VDD     || {{arrowr}}  || -5 Volts power supply
@@ Line 102: / Line 102: @@
 ''Note: Direction is computer relative device.''
+''Note: * = active low.''
+''Caution: Bit 0 being MSB is strange.''
 == Contributions ==
@@ Line 108: / Line 112: @@
 [[Category:Connector]]
+[[Category:Expansion]]